Strained Silicon High-K Metal Gate 22nm CMOS High Speed OR Gate
Shobha Sharma, Department of ECE, Indira Gandhi Delhi Technical University, Women (Delhi), India.
Manuscript received on 8 August 2013 | Revised Manuscript received on 18 August 2013 | Manuscript Published on 30 August 2013 | PP: 38-39 | Volume-3 Issue-3, August 2013 | Retrieval Number: C1092083313/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper demonstrates a high speed OR gate in CMOS technology with strained Silicon Metal gate 22nm technology node. The CMOS circuit uses forward body bias instead of reverse body bias which results in high speed .The excessive increase in forward body bias results in ouput level degradation. The simulations are done with HSPICE simulator with Arizona state University’s (USA) ‘HP ptm ’ model of level54. The average decrease in rise and fall time of output voltage is approximately 6% and decrease in propagation delay is 47 % in the forward body biased OR cmos gate. The present circuit can further be modified to preserve the output levels to their maximum levels inspite of very high Forward body bias in order to have higher speed, and this is the future scope of this paper.
Keywords: 22nm, High Speed AND Gate, CMOS AND Gate, Forward Body Biasing, Hi K Metal Gate Strained Si, Ptm Models.
Scope of the Article: High Speed Networks