Memristor: A Unique Discovery for Reducing Power
Vartika pandey1, Manisha Pattaniak2, R K Tiwari3

1Vartika Pandey*, Ph.D., Electronics from Jiwaji University, Gwalior.
2Manisha Pattaniak, Professor, ABV- Indian Institute of Information Technology and Management (ABV-IIITM) Gwalior.
3R K Tiwari, Associate at Regional Research Laboratory (CSIR), Bhopal.
Manuscript received on January 12, 2020. | Revised Manuscript received on January 22, 2020. | Manuscript published on February 10, 2020. | PP: 1183-1187 | Volume-9 Issue-4, February 2020. | Retrieval Number: C8171019320/2020©BEIESP | DOI: 10.35940/ijitee.C8171.029420
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Abstract: A Process parameter variation has increasing, which results unpredictable device behaviour, due to occurrence of deep submicron CMOS technology. As the time passage this issue is exasperated by low power requirements which are approaching transistor operation into sub threshold regime. Principally for portable devices efficient, capable and process variation amiable memory is the most demandable in the market. In designing of low power memories, leakage power is observant parameter to design low power devices, because leakage power plays a dominant role in the total power utilization of the devices. In this paper, simple 6T SRAM formed with memristor has compared with the technique based 6T SRAM for the various parameters like total power and leakage power. 
Keywords:  Vtcmos, Memristor, Forced Stack, Dtcmos.
Scope of the Article: Knowledge Discovery