High-Speed FIR Filter Design using Decision Tree Algorithm with FPGA Debugging
Murali Anumothu1, Kakarla Harikishore2

1Murali Anumothu*, Department of Electronics and Communication Engineering, K.L University, Vijayawada, India.
2Dr. Kakarla Harikishore Department of Electronics and Communication Engineering, K.L University, Vijayawada, India.
Manuscript received on December 14, 2019. | Revised Manuscript received on December 21, 2019. | Manuscript published on January 10, 2020. | PP: 764-770 | Volume-9 Issue-3, January 2020. | Retrieval Number: C8448019320/2020©BEIESP | DOI: 10.35940/ijitee.C8448.019320
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In recent years, the filter is one of the key elements in signal processing applications to remove unwanted information. However, traditional FIR filters have been consumed more resources due to complex multiplier design. Mostly the complexity of the FIR filter is dominated by multiplier design. The conventional multipliers can be realized by Single Constant Multiplication (SCM) and Multiple Constant Multiplication (MCM) algorithms using shift and add/subtract operations. In this paper, a hybrid state decision tree algorithm is introduced to reduce hardware utilization (area) and increase speed in filter tap cells of FIR. The proposed scheme generates a decision tree to perform shift & addition and accumulation based on the combined SCM/MCM approach. The proposed FIR filter was implemented in Xilinx Field Programmable Gate Array (FPGA) platform by using Verilog language. The experimental results of the DTG-FIR filter were averagely reduced the 48.259% of LUTs, 51.567 % of flip flops and 44.497 % of slices at 183.122 MHz of operating frequency on the Virtex-5 than existing VP-FIR. 
Keywords: FIR filter, Digital Signal Processing, Large Scale Integration, Power-area Product, Multiple Constant Multiplication, Low power.
Scope of the Article: System Integration