Design and Implementation of Full Adder using Different XOR Gates
D. Durga Prasad1, M. Dileep2, Ch. Rama Krishna3
1D.Durga Prasad, Assistant Professor, Department of ECE, Vishnu Institute of Technology, Vit, Bhimavaram, Andhra Pradesh, India
2M.Dileep , Associate Professor, Department of ECE, Vishnu Institute of Technology, Vit, Bhimavaram, Andhra Pradesh, India
3Ch.Rama Krishna, Associate Professor, Department of ECE, Vishnu Institute of Technology, Vit, Bhimavaram, Andhra Pradesh, India
Manuscript received on January 12, 2020. | Revised Manuscript received on January 22, 2020. | Manuscript published on February 10, 2020. | PP: 1422-1426 | Volume-9 Issue-4, February 2020. | Retrieval Number: C8891019320/2020©BEIESP | DOI: 10.35940/ijitee.C8891.029420
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Abstract: A Full Adder is a logical circuit that servers a great part in the design of application particular integrated circuits. It is the basic component found in VLSI and DSP applications. The applications of Full adder in VLSI include ALU design, Address generation in processors, Multipliers and so on. Power consumption is one of the most significant parameters of full adder. Therefore, reducing power consumption in full adder is very important. In this paper, Design XOR gate using Transmission gate logic (TGL), Pass transistor logic (PTL) and Static Complementary metal oxide semiconductor logic (CMOS). Also design Full Adder circuit using different XOR gate designs. These circuits are designed and implemented, simulated using Mentor Graphics Tool. After getting simulation results, compare the different XOR gate designs based full adders in terms of power consumption and delay. Using the comparative analysis for the designed Full Adders, an effective adder design can be chosen based on the performance criteria as required by the designer.
Keywords: Full Adder, TGL, PTL, Mentor Graphics Tool.
Scope of the Article: Computer Graphics, Simulation, and Modelling