FPGA Implementation of 64 Point FFT Processor
Vasantha Sudheer N1, Venu Gopal B2

1Vasantha Sudheer N, M.Tech Ece Department, JNTU Kakinada University, Kaushik College of Engineering, Visakhapatnam, India.
2Venu Gopal B, Assoc .Professor, Dept. of Ece, Kaushik College of Engineering, visakhapatnam, India.

Manuscript received on October 01, 2012. | Revised Manuscript received on October 20, 2012. | Manuscript Published on September 10, 2012. | PP: 63-66 | Volume-1 Issue-4, September 2012. | Retrieval Number: D0260081412/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: A power efficient Fast Fourier Transform (FFT) processor for use in the Direction of Arrival (DOA) estimation of a wideband waveform is presented. The target device for implementation is a Xilinx Spartan-3 Xc3s200 Field Programmable Gate Array (FPGA). The FFT processor was developed using the Xilinx ISE in Verilog code. Although the parallel and pipelined architecture uses a large portion of the available FPGA resources, the architecture does yield a high throughput. The total power cosumed by the design is 0.081W. 
Keywords: Direction of Arrival (DOA), Fast Fourier Tansform (FFT),FPGA.