Performance Comparison for Ripple Carry Adder Using Various Logic Design
G. Sasi1, G. Athisha2, S. Surya prakash3
1G. Sasi, Professor, Department of Electronics and Communication Engineering, Vallurupalli Nageswara Rao Vignana Jyothi Institute of Engineering &Technology, Hyderabad. Telangana, India.
2G. Athisha, Associate Professor, Department of Electronics and Communication Engineering, Vallurupalli Nageswara Rao Vignana Jyothi Institute of Engineering &Technology, Hyderabad. Telangana, India.
3S. Surya prakash, PG Student, Department of Electronics and Communication Engineering, Vallurupalli Nageswara Rao Vignana Jyothi Institute of Engineering &Technology, Hyderabad. Telangana, India.
Manuscript received on 05 March 2019 | Revised Manuscript received on 12 March 2019 | Manuscript Published on 20 March 2019 | PP: 372-377 | Volume-8 Issue- 4S2 March 2019 | Retrieval Number: D1S0081028419/2019©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: CMOS transistors are extensively used in designing digital circuits. Transistor level design is an important aspect in any digital circuit designs particularly in full adders. Full adder is the basic part in any of the arithmetic circuits. Fin FET is another technology that has a longer channel gate. Carbon Nanotube field effect transistor (CNTFET) is the most optimistic technology which is three terminal device similar to MOSFET. The semiconducting channel between the two contacts called drain and source consists of the nano tube. This paper presents Ripple carry adder (RCA) using static and dynamic logic styles with CMOS, Fin FET and CNTFET technologies in 20nm technology with supply voltage of 0.9v and simulation is done by using Synopsys HSPICE Tool.
Keywords: Ripple Carry Adder, Static and Dynamic Logic Styles, CNTFET, Fin FET and HSPICE Tool.
Scope of the Article: Communication