Design and Analysis of High Speed and Low Power Reversible Vedic Multiplier Incorporating with QSDN Adder
Karanam Deepak

KARANAM DEEPAK, Department of Electrical & Electronics Engineering, G. Pullaiah College of Engineering and Technology, Kurnool (A.P), India.
Manuscript received on 05 February 2019 | Revised Manuscript received on 13 February 2019 | Manuscript published on 28 February 2019 | PP: 273-279 | Volume-8 Issue-4, February 2019 | Retrieval Number: D2741028419/19©BEIESP
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Abstract: This present work deals with a reversible Vedic type multiplier using the earliest Urdhva Tiryagbhyam sutras of Vedic type mathematics combine with the QSD adder (Quaternary Signed digit number adder). There are three activities be intrinsic into duplication halfway items age, fractional items decrease and expansion. Quick snake design in this way enormously upgrades the speed of the general procedure. A pass on free math errand be able to be cultivated use a top radix number formation, for instance, QSD adder. In QSD, each one number can be address by a digit as of – 3 to 3. Pass on complimentary development as well as distinctive exercises on incalculable, for instance, 64, 128, or more can be executed with consistent deferment and less multifaceted nature. The proposed multiplier configuration is contrasted and a reversible Vedic multiplier consolidates a QSD Quaternary Signed digit number adder viper among a transformation section for quaternary to paired change. The proposition demonstrates a most extreme speed enhancement.
Keyword: Arithmetic Multiplier, Quaternary Signed Digit Adder [QSD], Urdhva Tiryagbhyam, Vedic Type Mathematics, Carry Free Addition, QSD, Redundancy.
Scope of the Article: High Speed Networks