FPGA based Pseudo Random Sequence Generator using XOR/XNOR for Communication Cryptography and VLSI Testing Applications
B. Murali Krishna1, G.L.Madhumati2, Habibulla Khan3

1B.Murali Krishna, Research Scholar, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram (A.P), India.
2G.L.Madhumati, Professor & HOD, Department of ECE, Dhanekula Institute of Engineering & Technology, Ganguru (A.P), India.
3Habibulla Khan, Professor & Dean, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram (A.P), India.
Manuscript received on 05 February 2019 | Revised Manuscript received on 13 February 2019 | Manuscript published on 28 February 2019 | PP: 485-494 | Volume-8 Issue-4, February 2019 | Retrieval Number: D2782028419/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Random number generators are most prominently used in the area of communication to provide security for information systems through pseudo random sequences. It also applicable for key generation in cryptography applications and signature analyzer to generate test patterns for Built-In-Self Test. In conventional method, random numbers are generated by a reference value i.e., seed value, using a XOR gate. The new proposed methods present a linear feedback shift register (LFSR) which generates an arbitrary number based on XOR, XNOR gates with and without seed value using multiplexer. Multiplexer is append to generate a random value at user defined state in runtime. Hardware complexity and power consumption is reduced by replacing the multiplexer with tristate buffers. Result analysis indicates that proposed LFSR with and without seed value gives a better performance, low power consumption and improves more randomness in runtime with Partial Reconfiguration (PR). Resource utilization for standard XOR based LFSR is compared with proposed LFSR using XOR and XNOR logic. Proposed method is designed in Verilog HDL, simulated with ISE Simulator, synthesized and implemented using Xilinx ISE, targeted for Spartan3E XC3S500E-FG320-4 and Virtex-5 XUPV5LX-110T architecture
Keyword: LFSR, XOR, XNOR, Multiplexer, Xilinx, PR, FPGA.
Scope of the Article: Agricultural Informatics and Communication