Design a Low Power and High Speed Parity Checker using Exclusive–or Gates
Brahmaiah Battula1, Valeti SaiLakshmi2, S. Durga Sri Sravya3, Putta Vijaya Lakshmi4, Sunanda Karpurapu5, S. Lakshmi Navya Sri6
1Brahmaiah Battula*, Department of ECE, JNTUK, Guntur, India.
2Valeti SaiLakshmi, Department of ECE, JNTUK, Guntur, India.
3S. Durga Sri Sravya, Department of ECE, JNTUK, Guntur, India.
4Putta Vijaya Lakshmi, Department of ECE, JNTUK, Guntur, India.
5Karpurapu Sunandha, Department of ECE, JNTUK, Guntur, India.
6S. Navya Sri, Department of ECE, JNTUK, Guntur, India.
Manuscript received on February 02, 2021. | Revised Manuscript received on February 08, 2021. | Manuscript published on February 28, 2021. | PP: 121-125 | Volume-10 Issue-4, February 2021 | Retrieval Number: 100.1/ijitee.D85220210421| DOI: 10.35940/ijitee.D8522.0210421
Open Access | Ethics and Policies | Cite | Mendeley
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In the presented paper we designed the parity checker by using EX-OR modules. The two EX-OR modules are presented to design the parity checker and correlated their outcomes based on the constraints like power, area, delay and power delay product (PDP). The previous design is with eight transistors EX-OR, but in the present six transistors EX-OR is used to design the parity checker. While correlating the parity checker design with 8T EX-OR and 6T EX-OR, the 6T EX-OR parity checker design gives optimized power, delay, area and PDP over the 8T EX-OR parity checker design. Simulations are done by using the 130nm mentor graphics tool. Finally the constraints like power, area, delay and PDP gets optimized successfully with the presented technology. Also, alternatively we can replace EXOR modules with NAND modules to design parity checker.
Keywords: Power Delay Product (PDP), Parity Checker, EX-OR modules, Mentor Graphics tool.