Delay-Optimistic Multiplier Design using Parallel Prefix Adder with Compressors
J. V. R Ravindra1, Chava Chaitanya2, Kasam Pranya3, Vaddem Sahiti4
1Dr. J.V.R. Ravindra, Principal and Professor, Vardhaman College of Engineering, Hyderabad (Telangana), India.
2Chava Chaitanya, Department of Electronics and Communication Engineering, Vardhaman College of Engineering, Hyderabad (Telangana), India.
3Kasam Pranya, Department of Electronics and Communication Engineering, Vardhaman College of Engineering, Hyderabad (Telangana), India
4Vaddem Sahiti, Department of Electronics and Communication Engineering, Vardhaman College of Engineering, Hyderabad (Telangana), India.
Manuscript received on 23 February 2023 | Revised Manuscript received on 27 February 2023 | Manuscript Accepted on 15 March 2023 | Manuscript published on 30 March 2023 | PP: 8-14 | Volume-12 Issue-4, March 2023 | Retrieval Number: 100.1/ijitee.D94750312423 | DOI: 10.35940/ijitee.D9475.0312423
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This article provides an illustration of the design process for 5-2 and 7-2 compressors operating at extremely high speeds. When compared to the prior designs, the new approach significantly reduced the gate-level delay while maintaining an appropriate overall transistor and gate count. With the help of 7:2 and 5:2 compressor infusion, when compared to earlier designs, the gate-level latency has been significantly decreased while the overall transistor and gate counts have remained within acceptable bounds. The technique was created for the 5-2 compressor and expanded for the 7-2 design, which exhibits higher speed performance enhancement for these architectures. To increase performance in terms of latency, we can switch out the ripple carry adder at the last addition for a parallel prefix adder. In addition, careful design considerations were taken to keep other factors, such as power and activity, within reasonable bounds. The best-reported circuits have also undergone redesigns, and the parasitic components of those circuits have been eliminated using the same method to produce a fair comparison. Using a common 16 × 16-bit multiplier, the performance of the built compressor blocks has also been assessed.
Keywords: 5-2 and 7-2 Compressors, Ripple Carry Adder, Parallel Prefix Adder, Parallel Multiplier, Increased Performance and Speed.
Scope of the Article: Parallel and Distributed Algorithms