Optimised Architecture Implementation of Bidirectional Scanning in FPGA for Television
Pushplata Sagar

Pushplata Sagar, M. Tech Scholar Mewar University, Rajasthan, India.
Manuscript received on 15 November 2012 | Revised Manuscript received on 25 November 2012 | Manuscript Published on 30 November 2012 | PP: 23-26 | Volume-1 Issue-6, November 2012 | Retrieval Number: E0316101612/15©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency, but during last decade there has been a tremendous advancement in the fields of FPGAs circuits. Today FPGA are very fast, high density, and low power, suitable for implementing any kind of application. Bidirectional scanning is one of the novel techniques used in television to avoid the retrace or fly back period of the electron beam. This saves power consumed by the beam during retrace period. RTL using Very High Speed Integrated Hardware Description Language (VHDL) is used to implement bidirectional scanning in FPGA. The functional and timing simulations of design are verified using Modelsim Simulator. Integrated software environment (ISE) from Xilinx is used to generate net-list from RTL code. The power consumption of the design is calculated using Xilinx power calculator.
Keywords: Bidirectional scanning, FPGA.

Scope of the Article: Discrete Optimization