Design and Analysis of a Low Power CMOS Sense Amplifier for Memory Application
Jyoti Hooda1, Sarita Ola2, Manisha Saini3
1Jyoti Hooda, Department of ECE, World College of Technology & Management, Gurgaon (Haryana), India.
2Sarita Ola, Department of ECE, World College of Technology & Management, Gurgaon (Haryana), India.
3Manisha Saini, Department of ECE, Meri College of Technology & Management, Gurgaon (Haryana), India.
Manuscript received on 15 April 2013 | Revised Manuscript received on 22 April 2013 | Manuscript Published on 30 April 2013 | PP: 271-279 | Volume-2 Issue-5, April 2013 | Retrieval Number: E0715042413/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper we design a low power high speed sense amplifier for CMOS SRAM. It has to sense the lowest possible signal swing from the SRAM bit lines and its response time should be very fast while keeping the power consumption within a tolerable limit. in this presented sense amplifier will be based on latest architectures available in literature and we focus will be to improve the power consumption and response time of this sense amplifier. Typical memory that is available has read access time of 12 ns and power consumption of 160 mW and supply voltage ranges from 1.8 to 3.3V and rise time SAEN signal ranges from 100 to 400ps and offset voltages ranges from 45 to 80mv. In this paper we present to improve access time power consumption two parameters of sense amplifier. Presented Sense amplifier CMOS SRAM all schematic are design tanner EDA S-edit , Simulate T-spice and 0.18µm technology
Keywords: Sense Amplifier, off Set in Sense Amplifier, Advanced Current Latched Sense Amplifier, Precharged Circuit.
Scope of the Article: Low-power design