Design and Implementation of Low Power Delay Locked Loop using Multiplexer Based Phase Frequency Detector
Vinayak U. Gandage1, Veena M. B.2
1Mr. Vinayak U. Gandage*, Department of Electronics and Communication Engineering, BMS College of Engineering, Autonomous University, Bangalore, India.
2Dr. Veena M. B., Department of Electronics and Communication Engineering, BMS College of Engineering, Autonomous University, Bangalore, India.
Manuscript received on February 10, 2020. | Revised Manuscript received on February 22, 2020. | Manuscript published on March 10, 2020. | PP: 951-955 | Volume-9 Issue-5, March 2020. | Retrieval Number: E2636039520/2020©BEIESP | DOI: 10.35940/ijitee.E2636.039520
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper proposes design and implementation of low power Delay Locked Loop Architecture, with dynamic Multiplexer based Phase Frequency Detector with minimum locking time. Clock and data recovery systems are employed to derive the clocking information to correctly decode the transmitted data at the receiver. Delay Locked Loop is one of the most important clock recovery systems. The DLL architecture is designed using Cadence Virtuoso 180nm Technology with 1.8V power supply. The proposed DLL with Multiplexer based phase frequency detector shows significant reduction in power dissipation by 10% compared to DLL designed using D-FF based PFD and achieves locking state within 10 clock cycles with minimum jitter of 4.84326ps, measured within clock frequency range of 100-250MHz.
Keywords: Delay Locked Loop (DLL), Phase Frequency Detector (PFD), Voltage Controlled Delay Line (VCDL), Area, Power Dissipation.
Scope of the Article: Frequency Selective Surface