Reduction of Test Time using Multiple Test Control Point Insertion for 7nm Technology Node
Maharshi Patel1, Yogesh Parmar2, Haresh Suthar3
1Maharshi Patel*, ECE, Parul University, Vadodara, Gujarat. India.
2Yogesh Parmar, Assistant Professor, Department of Electronics and Communication Engineering, Parul Institute of Technology, Vadodara, Gujarat. India.
3Haresh Suthar, Assistant Professor & HOD, Department of Electronics and Communication Engineering at Parul Institute of Technology, Vadodara, Gujarat, India.
Manuscript received on February 10, 2020. | Revised Manuscript received on February 26, 2020. | Manuscript published on March 10, 2020. | PP: 1957-1960 | Volume-9 Issue-5, March 2020. | Retrieval Number: E2946039520 /2020©BEIESP | DOI: 10.35940/ijitee.E2946.039520
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Test time reduction is a prominent challenge in scan based Design For Testability (DFT) architectures for cost effective test. Reliability and testability both are main objectives for DFT in today’s VLSI design. In this paper, we have proposed multiple standard test control point insertion technique for 7nm technology node. The design was tested on 7828 sequential cells. We have compared results of following three Design Rule Check (DRC) (1) Scan DRC (2) Clock Scan DRC (3) Multiple standard test control point insertion DRC. We have used software tool Synopsys Tetra MAX ATPG, Synopsys DFTMAX and Synopsys DFT compiler to verify the design. It has been observed that multiple standard test control point insertion DRC takes minimum time to check design of 7828 sequential cells.
Keywords: DRC, Scan Insertion, DFT, VLSI.
Scope of the Article: Renewable Energy Technology