CMOS Low Voltage LNA with Improved Noise Figure
Najeemulla Baig1, Fazal Noorbasha2
1Najeemulla Baig, Research Scholar, Department of Electronic Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur (A.P), India.
2Dr. Fazal Noorbasha, Associate Professor, Department of Electronic Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur (A.P), India.
Manuscript received on 17 April 2019 | Revised Manuscript received on 24 April 2019 | Manuscript published on 30 April 2019 | PP: 606-609 | Volume-8 Issue-6, April 2019 | Retrieval Number: E3119038519/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: IIn this research paper the designing of 1.5754GHz low Noise Amplifier integrated with a 90nm CMOS process using RF-spectre is presented. The intended circuit exhibits power gain of 19.82dB; S12 of -31.10dB, noise figure of 0.462mdB, 1-dB compression point of -14.57mdB and IIP3 equal to -12.557mdB at low power supply of 0.7 V.
Keyword: Low Noise Amplifier (LNA), Global positioning system (GPS), Impedance matching, Noise figure (NF), 3 rd order input intercept point (IIP3) Gain.
Scope of the Article: Low Noise Amplifier