Design of a 4 bit Arithmetic and Logical unit with Low Power and High Speed
C.Arunabala1, Ch. Jyothirmayi2, D N S V Sreeja.T3, Suma Burra4, Hrithika Reddy Udumula5, I.R.Anusha Devi6

1Dr. C. Arunabala*, E.C.E, JNTUK, Guntur, India.
2Ch.Jyothirmayi, E.C.E, JNTUK, Guntur, India.
3D N S V Sreeja.T, .C.E, JNTUK, Guntur, India.
4Suma Burra, Hrithika .C.E, JNTUK, Guntur, India.
5Udumula, .C.E, JNTUK, Guntur, India.
6I.R. Anusha Devi, E.C.E, JNTUK, Guntur, India.

Manuscript received on March 13, 2021. | Revised Manuscript received on March 22, 2021. | Manuscript published on March 30, 2021. | PP: 87-92 | Volume-10 Issue-5, March 2021 | Retrieval Number: 100.1/ijitee.E86600310521| DOI: 10.35940/ijitee.E8660.0310521
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Abstract: In this presented work we designed the 4- bit Arithmetic & Logical Unit (ALU) by using the different modules. The Various modules are AND gate & OR gate designed with six transistors, While the XOR modules is designed with both eight transistors & six transistors. The six transistor XOR module gives optimized results. Another one is the four by one multiplexer designed with eight transistors implemented using Pass transistor logic (PTL) style. The full adder module is designed by using 18 transistors implemented through PTL style. Here because of PTL style the number of transistor count optimized such that the constraints get optimized results. By using the AND, OR, XOR, 4X1 MUX and full adder modules with reduced transistor count we designed the one bit ALU. With one bit ALU we designed 4 bit ALU and compared the outcomes with conventional 4 bit ALU design so that the proposed 4 bit ALU design has optimized transistor count, area, power, delay and power delay product (PDP). Simulations are verified through 130nm mentor graphics tool. 
Keywords: Pass Transistor Logic (PTL) style, power delay product (PDP), Arithmetic and logic unit (ALU), mentor graphics tool.