Design of Various Low Power and Highspeed Full Adder Designs using 45nm Cmos Technology
Soniya Nuthalapati1, Ch. Jyothirmayi2, Galla. Saikiran3, Chaitanya Prathikonda4, Arigala Joseph Jagarlamudi Manikanta5

1Soniya Nuthalapati*, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India. 
2Ch. Jyothirmayi, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India. 
3Galla. Saikiran, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India.
4Chaitanya Prathikonda, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India. 
5Arigala Joseph Jagarlamudi Manikanta, Department of Electronics & Communication Engineering, Jawaharlal Nehru Technological University, Kakinada. Guntur (A.P), India. 
Manuscript received on 29 March 2022. | Revised Manuscript received on 04 April 2022. | Manuscript published on 30 April 2022. | PP: 21-26 | Volume-11 Issue-5, April 2022. | Retrieval Number: 100.1/ijitee.E98480411522 | DOI: 10.35940/ijitee.E9848.0411522
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Abstract: This project visualizes the different designs of Full Adder (FADDR) circuits. These FADDR circuits are designed mainly to reduce the power and delay factors. If these two factors are minimized then automatically the power delay product (PDP) gets minimized. In addition, to design the FADDR, we used multiplexer. So, that the FADDR transistor count gets reduced. Here in this FADDR implementation, it is designed with different transistors count and the factors like power consumption propagation delay and power delay product (PDP) constraints are tabulated with different transistor count of FADDR designs. Then the power consumption and propagation delay factors get reduced. The designs are simulated by using 45nm CMOS technology in Cadence Virtuoso tool. 
Keywords: Index Terms: Power Consumption, Propagation Delay, 45nm Cmos Technology and Cadence Virtuoso Tool.
Scope of the Article: Low-power design