256K Memory Bank Design with 9T SRAM Bit Cell and 22nm CNTFET Optimizing for Low Power and Area
Y. Maheswar1, B.L. Raju2, K. Soundara Rajan3

1Y.Maheswar, Research Scholar, Department of Electronics and Communications Engineering, JNTU Anantapuramu, Andhra Pradesh, India.

2B.L.Raju, Principal,  Angiotensin Converting Enzyme College of Engineering & Tech, India.

3K.Soundara Rajan, Principal, TKR College of Engineering & Tech. Sciences, India.

Manuscript received on 05 March 2019 | Revised Manuscript received on 17 March 2019 | Manuscript Published on 22 March 2019 | PP: 675-681 | Volume-8 Issue-5S April 2019 | Retrieval Number: ES3503018319/19©BEIESP

Open Access | Editorial and Publishing Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In this paper, 9T bit cell is designed along with its periphery circuits to enhance the operating speed of 256 Kb memories. 9T SRAM bit cell is designed with 22nm FINFET technology to obtain optimum bit cell transistor geometry. For variations in transistor geometries, VDD and temperature, the leakage current for the designed bit cell is estimated. The peripheral circuitry transistor geometries are designed for applications with low power and high speed. 9T bit cell integrated with its periphery is designed to form 256 Kb memory with two 128 Kb memory banks.

Keywords: Sub Threshold SRAM, Current Sense Amplifier, High Speed, Cross Coupled Inverter, 9T bit cell, CNTFET.
Scope of the Article: Communication