Implementation of Multiplier using Vedic Algorithm
Poornima M1, Shivaraj Kumar Patil2, Shivukumar3, Shridhar K P4, Sanjay H5

1Poornima M, Assistant Professor, MVJCE, Bangalore (Karnataka), India.
2Shivuraj Kumar Patil, Department of ECE, MVJCE, Bangalore (Karnataka), India.
3Shivukumar, Department of ECE, MVJCE, Bangalore (Karnataka), India.
4Shridhar K.P, Department of ECE, MVJCE, Bangalore (Karnataka), India.
5Sanjay H, Department of ECE, MVJCE, Bangalore (Karnataka), India.
Manuscript received on 10 May 2013 | Revised Manuscript received on 18 May 2013 | Manuscript Published on 30 May 2013 | PP: 219-223 | Volume-2 Issue-6, May 2013 | Retrieval Number: F0839052613/13©BEIESP
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Abstract: Vedic mathematics is the name given to the ancient Indian system of mathematics that was rediscovered in the early twentieth century from ancient Indian sculptures (Vedas). This paper proposes the design of high speed Vedic Multiplier using the techniques of Vedic Mathematics that have been modified to improve performance. A high speed processor depends greatly on the multiplier as it is one of the key hardware blocks in most digital signal processing systems as well as in general processors. Vedic Mathematics has a unique technique of calculations based on 16 Sutras. This paper presents study on high speed 8×8 bit Vedic multiplier architecture which is quite different from the Conventional method of multiplication like add and shift. Further, the Verilog HDL coding of Urdhva tiryakbhyam Sutra for 8×8 bits multiplication and their FPGA implementation by Xilinx Synthesis Tool on Spartan 3 kit have been done and output has been displayed on LED’s of Spartan 3 kit .
Keywords: Architecture, Ripple Carry (RC) Adder, Multiplication, Vedic Mathematics, Vedic Multiplier (VM), Urdhava Tiryakbhyam Sutra.

Scope of the Article: Web Algorithms