Design and Implementation of Low Power 4:1 Multiplexer using Adiabatic Logic
Sarita1, Jyoti Hooda2, Shweta Chawla3

1Sarita Ola, Department of ECE, World College of Technology & Management, Gurgaon (Haryana), India.
2Jyoti Hooda, Department of ECE, World College of Technology & Management, Gurgaon (Haryana), India.
3Shweta Chawla, Department of ECE, B.M. College of Technology & Management, Gurgaon (Haryana), India.
Manuscript received on 10 May 2013 | Revised Manuscript received on 18 May 2013 | Manuscript Published on 30 May 2013 | PP: 224-227 | Volume-2 Issue-6, May 2013 | Retrieval Number: F0840052613/13©BEIESP
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Abstract: The main and highly concerned issue in the low power VLSI design circuits is Power dissipation. The basic approaches that we used for reducing energy/power dissipation in conventional CMOS circuits include reducing the supply voltages, on decreasing node capacitances and minimize the switching activities with efficient charge recovery logic. The Adiabatic switching technique based upon the energy recovery principle is one of the techniques which is widely used to achieve low power VLSI design circuits. In the following paper the power dissipation of various adiabatic circuits is calculated and then simulated using T-SPICE tool. From the results of calculation it is observed that among all of the techniques used for multiplexer implementation the efficient charge recovery logic (ECRL) multiplexer exhibits the minimum power dissipation. The adiabatic logic family has been proposed by implementing PMOS and NMOS transistors as pull down network and pull up network. With the help of calculated result, it has been shown that the multiplexer used with adiabatic logic can reduce the power dissipation than conventional CMOS circuit.
Keywords: Adiabatic, VLSI, ECRL, T-SPICE.

Scope of the Article: Digital System and Logic Design