Comparison of Power Consumption in Array Multiplier with and without SVL Circuit
K. Raja Kumari1, S. Leela Lakshmi2
1K.Raja Kumari, Student M.Tech, Srikalahasteeswara Institute of Technology, JNTU Anantapur, Tirupati (Andhra Pradesh), India.
2S.Leela Lakshmi, Assistant Professor Sr, Srikalahasteeswara Institute of Technology, JNTU Anantapur, Tirupati (Andhra Pradesh), India.
Manuscript received on 10 November 2013 | Revised Manuscript received on 18 November 2013 | Manuscript Published on 30 November 2013 | PP: 80-83 | Volume-3 Issue-6, November 2013 | Retrieval Number: F1337113613/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper, we performed the comparative analysis of power consumption of array multiplier circuit implemented with two adder modules and Self Adjustable Voltage level circuit (SVL). The adder modules chosen were 10 transistor- Static Energy Recovery CMOS adder and 8 transistor CMOS (SERF) circuits. At first, the circuit was simulated with adder modules without applying the SVL circuit. And secondly, SVL circuit was incorporated in the adder modules for simulation. In the multiplier architecture chosen, less power consumption was observed being consumed by the SERF adder based multipliers applied with SVL circuit.
Keywords: 10 Transistor SERF Adder, 8 Transistor Adder, SVL Circuit.
Scope of the Article: Low-power design