High Performance Reversible Vedic Multiplier Using Cadence 45nm Technology
S. Prema1, Ramanan.S.V2, R. Arun Sekar3, Rajan Cristin4
1S.Prema, Department of ECE, SNS College of Technology,Coimbatore (Tamil Nadu), India.
2Ramanan.S.V, Department of ECE, PPG Institute of Technology,Coimbatore (Tamil Nadu), India.
3R. Arun Sekar, Department of ECE, GMR Institute of Technology,Rajam (Andhra Pradesh), India.
4Rajan Cristin, Department of CSE, GMR Institute of Technology,Rajam (Andhra Pradesh), India.
Manuscript received on 01 May 2019 | Revised Manuscript received on 15 May 2019 | Manuscript published on 30 May 2019 | PP: 47-52 | Volume-8 Issue-7, May 2019 | Retrieval Number: F3502048619/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Vedic science is an antiquated strategy of Indian arithmetic as it contains 16 Sutras. A fast 16 *16 multiplier configuration is designed utilizing Urdhva Tiryakbhyam sutra is introduced in this work. By utilizing this sutra the fractional items and entireties are created in single stage which decreases the structure of design in processors. By utilizing this method we can diminish the delay to the maximum extent when contrast with cluster or corner multiplier. By utilizing this strategy we lessen the inciting delay in connection with bunch based plan and parallel carry based use which are most normally used models. The essential significance of this paper is the delay and dynamic power usage is found to be diminished
Keyword: Wallace tree multiplier, Vedic multiplier (VM), Reversible logic.
Scope of the Article: Renewable Energy Technology.