Implementation of Asynchronous FIFO using Low Power DFT
Avinash Yadlapati1, K Hari Kishore2

1Avinash Yadlapati, Research Scholar, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India.

2K Hari Kishore, Professor, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India.

Manuscript received on 04 April 2019 | Revised Manuscript received on 11 April 2019 | Manuscript Published on 26 April 2019 | PP: 152-156 | Volume-8 Issue-6S April 2019 | Retrieval Number: F60420486S19/19©BEIESP

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Abstract: An Asynchronous FIFO or First-in-First-out is a digital circuit to store data and to synchronize data transfers between two different clock domains. When data transfer happens between two different clock domains, it is very important to ensure that data is properly synchronized between the transmitter and the receiver so that no data is lost during the transfer. In any Asynchronous FIFO Design, data is written sequentially into the FIFO buffer in one clock domain and then the data values are read sequentially from the same FIFO buffer using another clock domain, where the two clock domains are asynchronous to each other. Asynchronous FIFO’s are one of the most important building blocks for any System-on-Chip (SOC) Designs as they are the most widely used IP Blocks in multi-clock domain designs. In any SoC, low power has been the biggest challenge for any designer. Many low power techniques have come up at different phases of the design viz., Register Transfer Logic (RTL), Functional Verification, Logic Synthesis, Design for Test (DFT)and Physical Design. The two main areas in DFT where power has been a challenge is during the Scan Insertion Phase and during the Automated Test Patter Generation (ATPG) phase. Due to the additional scan circuitry being inserted during the testing phase, the power utilization has increased. Hence, the need for Low Power DFT techniques has arisen in all the SoC’s that are being designed. In this paper, the primary focus has been on reducing the power for an Asynchronous FIFO at the DFT phase. The RTL Code is written in Verilog and synthesized using Synopsys Design Compiler. The aim of the experiment is to perform the low power DFT on the Asynchronous FIFO Net list and to compare the power reduction after applying the low power DFT technique and before applying the low power DFT technique. The Scan clock frequency is halved to reduce the power in the circuit without affecting any timing violations. As the Scan Clock frequency is low, it can be further reduced within permissible limits of the specifications to ensure that dynamic power is reduced without affecting the testing process of the chip.

Keywords: Low power DFT (Design for Test); UPF; CPF; Asynchronous FIFO; Scan Circuitry; Clock Gating; ATPG (Automatic Test Pattern Generation); Scan Clock; Net list; Pointers; SoC.
Scope of the Article: Low-power design