Leakage Reduction and Stability Improvement Techniques of 10T Sram Cell: a Survey
A. Veera Lakshmi1, S. Priya2

1A.VeeraLakshmi, Assistant Professor, Department of ECE, Sree Sastha Institute of Engineering and Technology, Chembarampakkam, Chennai (Tamil Nadu), India.
2S.Priya, Assistant Professor, Department of ECE, Lord Iyappa Institute of Engineering and Technology, Uthukadu, Kancheepuram (Tamil Nadu), India.
Manuscript received on 8 December 2013 | Revised Manuscript received on 18 December 2013 | Manuscript Published on 30 December 2013 | PP: 148-153 | Volume-3 Issue-7, December 2013 | Retrieval Number: G1396123713/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Reduction of leakage power is very important for low power applications. Because these high leakage currents are the major contributor of total power consumption of the circuit. This paper explains about various leakage reduction techniques as well as stability improvement techniques of the different SRAM cells. Some of the leakage reduction techniques discussed in this paper are dynamic VDD, multiple Vth, SVL (Self- Controllable Voltage Level) and AVL( Adaptive Voltage Level). The stability improvement techniques are word-line adjustment, dual voltage supply, NBL (Negative Bit line) and bit interleaving technique. These techniques are applied on different SRAM cells (6T, 7T, 8T and 10T) and the results are compared. For simulation, MICROWIND 3.1 tool is used.
Keywords: Leakage Reduction, Write Ability, SRAM, Leakage Power.

Scope of the Article: Knowledge Engineering Tools and Techniques