FPGA Implementation of AES Algorithm
R. Sharadha1, CH. Bhanu Prakash2, M. J. C. Prasad3

1R. Sharadha, M.Tech, Department of Digital Systems & Computer Electronics, Mallareddy Engineering College, Secunderabad (Telangana), India.
2CH. Bhanu Prakash, Assistant Professor, Department of  Electronics and Communication Engineering, Malla Reddy Engineering College, Hyderabad (Telangana), India.
3Dr. M.J.C Prasad, Head, Department of Electronics and Communication Engineering, MREC, Secunderabad (Telangana), India.
Manuscript received on 8 December 2013 | Revised Manuscript received on 18 December 2013 | Manuscript Published on 30 December 2013 | PP: 102-108 | Volume-3 Issue-7, December 2013 | Retrieval Number: G1398123713/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: This paper presents the FPGA implementation of AES algorithm Cryptography is the science of secret codes, enabling the confidentiality of communication through an insecure channel. It protects against unauthorized parties by preventing unauthorized alteration of use. Generally speaking, it uses a cryptographic system to transform a plaintext into a cipher text, using most of the time a key. To increase the computational speed parallelism and pipelining architecture have been implemented. The simulation is done using Xilinx 13.2 version.
Keywords: AES, FPGA, Encryption, Decryption, Rijndael, Block Cipher.

Scope of the Article: Algorithm Engineering