Lower-Error Antilogarithmic Converters using Binary Error Searching Schemes
Chao-Tsung Kuo1, Tso-Bing Juang2

1Chao-Tsung Kuo, Department of Electronic Engineering, National Quemoy University, Kinmen Taiwan.
2Tso-Bing Juang, Department of Computer Science and Information Engineering, National Pingtung Institute of Commerce, Pingtung Taiwan.
Manuscript received on 8 December 2013 | Revised Manuscript received on 18 December 2013 | Manuscript Published on 30 December 2013 | PP: 95-101 | Volume-3 Issue-7, December 2013 | Retrieval Number: G1397123713/13©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In this paper, lower-error and ROM-free antilogarithmic converters with multiple regions of piecewise-linear approximation are proposed. By employing Binary Error Searching schemes, the error percent ranges of our proposed antilogarithmic converters could achieve 1.6808%, 0.5681%, 0.137% and 0.098% for 2-region, 4-region, 8-region and 16-region approximations respectively, which can outperform previously proposed methods in the literature. Area comparisons with previously well-known antilogarithmic converter using six-region approximation methods in the literature, our proposed antilogarithmic converter with four-region approximation can provide 1.7x error reduction with only 30% extra hardware overhead under the same delay constraints. These antilogarithmic converters are all designed and synthesized using TSMC 0.18 m process. Our proposed converters can be applied in the real-time 3-D graphics and DSP computations to ease the tremendous computation efforts.
Keywords: Antilogarithm, Logarithm, Computer Arithmetic, Very Large Scale Integration (VLSI) Design.

Scope of the Article: VLSI Algorithms