FPGA Implementation of AES for Image Encryption and Decryption
Vijayakumar P1, Chaitanya Kumar Chittoju2, A.V. Bharadwaja3, Payal P. Tayade4, Tamilselvi M5, R. Rajashree6, Xiao-Zhi Gao7

1P. Vijayakumar, School of Electronics Engineering, VIT Chennai, Tamilnadu, India.
2Chaitanya Kumar Chittoju, Electronics Engineering, Vellore Institute of Technology, Chennai, India.
3A.V. Bharadwaja, Department of ECE, GIET Autonomous College of Engineering and Technology, Andhra Pradesh, India.
4Payal P. Tayade, School of Electronics Engineering, VIT Chennai, Tamilnadu, India.
5M. Tamilselvi, Department of Mechatronics, T.S Srinivasan Centre for Polytechnic and Advanced Training, Chennai, India.
6R. Rajashree, Department of ECE, Dr. SJS Paul Engineering (Former), Pondicherry, India.
7Xiao-Zhi Gao, University of Eastern Finland, Finland.
Manuscript received on 05 May 2019 | Revised Manuscript received on 12 May 2019 | Manuscript published on 30 May 2019 | PP: 807-812 | Volume-8 Issue-7, May 2019 | Retrieval Number: G5706058719/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Information is the key source to mankind and securing it is the biggest task. Unauthorized access of information deals with the security. For securing the data many cryptographic lgorithmshasbeenproposed,fromallofthealgorithms Advanced Encryption Standard (AES) is one of the most widely used algorithm for data encryption and decryption. Many researchers have put their effort to develop a new prototype of cryptographic algorithm and triedtoimplementinFPGAsystem.AESisanetworkof all possible cases of data are scramble, which has mathematical operations performed and itseach output bit depends on every input bit. The encryption process and the decryption process of image isdone with using AES 128 bit encryption algorithm. The m*n image data is turned into a binary or hexadecimal format by using MATLABsyntaxandcreatea textfile.Byusingthis text file as an input and cipher text is fed to the AES for encryption and decryption process. The entire design is functionally simulated using ModelSim-Altera 6.4a. Implementation and other parameters were analyzed using Xilinx ISE synthesis tools. The results were analyzes using device Virtex-6 XC6VLX240T FPGA kit with Xilinx ISE14.7. 
Keyword: Advanced Encryption Standard; Field Programmable Gate Array; Cipher; AES Encryption; AES decryption; MATLAB; Image
Scope of the Article: Encryption Methods and Tools