Low Power Bidirectional Voltage Level Translator using Power Gating
Smt. Y. Sujatha

Y.Sujatha, ECE Department, Sri Vasavi Engineering College, Tadepalligudem, India.

Manuscript received on April 20, 2020. | Revised Manuscript received on April 29, 2020. | Manuscript published on May 10, 2020. | PP: 977-981 | Volume-9 Issue-7, May 2020. | Retrieval Number: G5729059720/2020©BEIESP | DOI: 10.35940/ijitee.G5729.059720
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Now a day’s, the demand for SoC based systems increasing. In SoC environment, multiple supply voltages are required because various subsystems of the system operate with different supply voltages. The communication between these systems is difficult and increases power consumption. The solution to this problem is to use a Voltage level translator/shifter between them. In this paper, a low power voltage level translator using power gating is proposed. By using this translator bidirectional voltage translator is implemented. In bidirectional voltage level translator, the data is translation between core logic and pad drivers and vice versa is possible with reduced power consumption and delay. In this paper, the power consumption reduces from 104uw to 6.25 pw at Vdd 1.8V. Delay is reduced from 19ns to 0.2 ns. 
Keywords:  Multiple supply domains, Pass transistor logic, Voltage level translator, Power gating.
Scope of the Article: Low-power design