Design of Efficient 16 Bit Crc with Optimized Power and Area in Vlsi Circuits
B.Balaji1, N Ajaynagendra2, Erigela Radhamma3, A Krishna Murthy4, M Lakshmana Kumar5

1B.Balaji, Associate Professor ECE, KLEF, Vijayawada, India.
2N. Ajay Nagendra, Assistant Professor ECE, KLEF, Vijayawada (A.P), India.
3E. Radhamma, Associate Professor ECE, BRIL, Hyderabad, India.
4A. Krishna Murthy, Associate Professor, PETW, Hyderabad, India.
5M.Lakshmana Kumar, Assistant Professor ECE, KLEF, Vijayawada(A.P), India.
Manuscript received on 02 June 2019 | Revised Manuscript received on 10 June 2019 | Manuscript published on 30 June 2019 | PP: 87-91 | Volume-8 Issue-8, June 2019 | Retrieval Number: G5993058719/19©BEIESP
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Abstract: In Very-Large-Scale Integration (VLSI) application power and area are the vital factors for any digital circuits. This paper presented 16 bit Cyclic Redundancy Check (C RC) mapped in version v14.20-s013 1 of Cadence Encounter(R) RTL Compiler. The codes in numerous instances are visible to be advanced at block lengths of realistic hobby when they’re used on low-noise BCCs.. By expeditiously mapping on cadence tool, Power is achieved small. The results of conversion are viewed mistreatment RTL synthesis cadence VIRTUOSO at 45nm technology. Supported digital signal process (DSP) architectures, the code for proposed low power is generated mistreatment 16 bit Cyclic Redundancy Check (CRC).
Keyword: 16 bit Cyclic Redundancy Check (CRC), Low Power, Low Area, High Level Synthesis, DSP, LUTs VLSI.
Scope of the Article: Low-power design