Design and Performance Evaluation of Hybrid Vedic Multipliers
Jami Venkata Suman

Jami Venkata Suman, Assistant Professor, Department of ECE, GMR Institute of Technology, Rajam, India.
Manuscript received on 02 June 2019 | Revised Manuscript received on 10 June 2019 | Manuscript published on 30 June 2019 | PP: 1622-1626 | Volume-8 Issue-8, June 2019 | Retrieval Number: G6120058719/19©BEIESP
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Abstract: Multipliers are one of the essential building blocks of several computational units. The computational units speed is determined by the multipliers speed. To improve the computational units speed, faster multiplier must be necessary. The Vedic multiplier is competent of performing faster multiplication operations. In Vedic mathematics, Urdhva Tiryakbhayam (UT) sutra discards the non essential steps in multiplication operation which in turn increases the speed performance of a multiplier. In this paper, design and performance evaluation of hybrid 8-bit and 16-bit UT Vedic multipliers are presented. The performances of proposed hybrid UT Vedic multipliers are improved by reducing the garbage outputs, constant inputs, quantum cost, number of total gates, Total Reversible Logic Implementation Cost (TRLIC), LUT’s, consuming power and improving speed compared with other existing conventional and reversible UT multipliers.
Keyword: Urdhva Tiryakbhayam, Vedic mathematics, quantum cost, constant inputs, garbage outputs, Verilog HDL, Xilinx Vivado design suite.
Scope of the Article: Cross Layer Design and Optimization.