Design of PLL with VCO of 40MHz-1 4GHz Ultra Low Phase Noise-120dBc/Hz Very Low RMS Jitter<180aS
N. Leela Krishna Sai1, M. Parthasarathy2, RayamSumanth3, R. Saktivel4
1N. Leela Krishna Sai, M.Tech Student, School of Electronics Engineering, Vellore Institute of Technology, Vellore (Tamil Nadu), India.
2M. Parthasarathy, M. Tech Student, School of Electronics Engineering, Vellore Institute of Technology, Vellore (Tamil Nadu), India.
3Rayam Sumanth, M.Tech Student, School of Electronics Engineering, Vellore Institute of Technology, Vellore (Tamil Nadu), India.
4Dr. R. Saktivel, Professor, School of Electronics Engineering, Vellore Institute of Technology, Vellore (Tamil Nadu), India.
Manuscript received on 01 May 2019 | Revised Manuscript received on 15 May 2019 | Manuscript published on 30 May 2019 | PP: 2002-2007 | Volume-8 Issue-7, May 2019 | Retrieval Number: G6255058719/19©BEIESP
Open Access | Ethics and Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents the design of Phase Locked Loop(PLL) with Voltage Controlled Oscillator(VCO) of 40Mhz—1.4GHz, ultra-low phase noise -120dBc/Hz, very low Root Mean Squared(RMS) Jitter <180aS by using 180-nm CMOS technology through Cadence Virtuoso Environment. In this paper, comparison between VCO designed with PMOS load ring VCO and Current starved VCO is shown. PMOS load ring VCO has an average power dissipation of 29.31 uW and with an oscillating frequency of 820 MHz. While Current Starved VCO has an average power dissipation of 20uW and with oscillating frequency of 1.17GHz. Phase Frequency divider(PFD) is made of resettable D–flipflops which uses a different structure rather than the conventional one with lower transistor count. PFD along with charge pump is used to reduce finite phase errors. Asynchronous frequency divider circuit is used with new structure of D-flipflop in which area and power dissipation reduces by 41.66% and 58.4%. The total average power dissipation and RMS Jitter of PLL with PMOS load ring VCO designed is 13.68 mW and 1.87as respectively and PLL with current starved VCO is 8.68mW and 31.24zs respectively. By varying control voltage of VCO from 0.4V to 1.6V, the tuning range from 28.2MHz-1.66GHz is attained.
Keyword: Current Starved VCO, Frequency Divider, Phase Locked loop (PLL), Root Mean Square (RMS) Jitter, Voltage Controlled Oscillator (VCO).
Scope of the Article: Low-power design.