Design of the High-speed Error-Trapping Decoder for the (693, 676) Fire Code
Jae-Yeon Choi

Jae-Yeon Choi, Department of Information and Communication Engineering, Namseoul University, Cheonan-City, Korea, East Asia.

Manuscript received on 10 June 2019 | Revised Manuscript received on 17 June 2019 | Manuscript Published on 22 June 2019 | PP: 651-654 | Volume-8 Issue-8S2 June 2019 | Retrieval Number: H11090688S219/19©BEIESP

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Abstract: In this paper, we design the decoder of (693, 676) Fire code for correcting burst-error which often occurs in wireless communication and storage system. Methods/Statistical analysis: The code length is determined by the generator polynomial which is based on the irreducible polynomial over Galois Field. Two shift registers for trapping error is included in an alternate (693, 676) Fire code decoding circuit, the error-tracking register and the error-pattern register based on the irreducible polynomial. The syndromes are calculated in the shift registers using irreducible polynomials, respectively. Findings: The prerequisites for code design are described first, and the Fire code for simple single burst error correction is mentioned. The high speed error trapping technique is suggested in the decoding system, and the operation of error pattern register and error tracking register is stated. Improvements/Applications: The speed and simplicity cannot be achieved at the same time, some trade-off must be made. The syndrome calculation can be achieved in the designed decoder by the simple cyclic shifts.

Keywords: Fire Code, Burst Error Correction, Error Trapping Decoder, Error Tracking Technique, Irreducible Polynomial.
Scope of the Article: Communication