Implementation of Digital Cross Connect For Simplex Mode of Communication
Chitra Sree P1, Ravi Shankar J2
1Chitra Sree P, Department of Electronics and Communication Engineering, SJB Institute of Technology, Bangalore (Karnataka), India.
2Ravi Shankar J, Department of Electronics & Communication Engineering, Venus Technologies, Bangalore (Karnataka), India.
Manuscript received on 11 January 2014 | Revised Manuscript received on 20 January 2014 | Manuscript Published on 30 January 2014 | PP: 66-69 | Volume-3 Issue-8, January 2014 | Retrieval Number: H1435013814/14©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: DCS available in the market is expensive and bulky and not scalable and reprogrammable. We have simulated various DCS modes, mainly concentrates on developing indigenous SOC architecture that is reprogrammable, scalable and upgradable. The various switching modes of proposed DCS are round robin, priority and request and acknowledge , The design is simulated using Verilog Hardware Description Language (HDL) in Xilinx ISE9.1i version software and can be implemented on Xilinx Spartan2 family based FPGA board.
Keywords: Telecommunication, Switching, DCS, Simplex Mode, Round Robin, Priority, Request And Acknowledge.
Scope of the Article: Communication