Design of Low Power Optimized Filter Architecture using VLSI Technique
Pritesh R. Gumble1, S.A. Ladhake2

1Pritesh R. Gumble, Department of Electronics and Telecommunication Engineering Sipna College of Engineering and Technology, Amravati Maharashtra State, India.
2Dr. S.A.Ladhake, Principal, Sipna College of Engineering and Technology, Amravati, Maharashtra State, India.

Manuscript received on 15 January 2015 | Revised Manuscript received on 21 January 2015 | Manuscript Published on 30 January 2015 | PP: 18-22 | Volume-4 Issue-8, January 2015 | Retrieval Number: H1950014815/15©BEIESP
Open Access | Editorial and Publishing Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (

Abstract: In the prevalence of DSP applications the weighted operations are the multiplication and accumulation. Multiplier-Accumulator (MAC) unit that consumes low power is always a means to accomplish a high concert digital signal processing system. Finite impulse response (FIR) filters are widely used in various DSP applications where signal were present with noise (e.g. data converters). Uptill many proficient techniques have been introduced for the design of low snag bit-parallel multiple constant multiplications (MCM) process which reduces the intricacy of many digital signal processing systems. On the other hand, digit-serial adder architectures present remarkable n-bit designs which process dynamic size data, since digit-serial operators hold less area and power. The purpose of this work is to design and implementation of low power optimized digital Finite impulse response (FIR) filter architecture using VLSI technique. We design and analyze 1] Direct form 2] Transpose form 3] Transpose using MCM 4] Transpose using digit serial adder 5] Transpose using MCM and digit serial adder. Experimental results shows the efficiency of the various architectures and we found best performance results of Transpose using MCM and digit serial adder design in terms of area and power. To execute this work the design is verified using Active-HDL with MATLAB and synthesis [45nm] using Synopsys.
Keywords: Digit- Serial adder Architecture, FIR, Low Power, MAC, MCM.

Scope of the Article: Computer Architecture and VLSI