A Low Power 6T-Auto Awake Mode-SRAM Design for high speed storage application
B. Satheesh1, Prabhu Benakop2

1B. Satheesh, Research Scholar , Dept of ECE, jntu Hyderabad, Telangana State, India,
2Prabhu Benakop, Dept of ECE, Methodist College of Engineering and Technology, Hyderabad, Telangana State, India

Manuscript received on 30 June 2019 | Revised Manuscript received on 05 July 2019 | Manuscript published on 30 July 2019 | PP: 204-208 | Volume-8 Issue-9, July 2019 | Retrieval Number: H6606068819/19©BEIESP | DOI: 10.35940/ijitee.H6606.078919
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In the digital world, Static Random Access Memory (SRAM) is one of the efficient core component for electronics design, it consumes huge amount of power and die area. In this research, the SRAM design analysis in terms of read margin, write margin and Static Noise Margin (SNM) for low power application is considered. In SRAM memory, both read and write operation affect by noise margin. So, read and write noise margins are considered as the significant challenges in designing SRAM cell. In this research, robust 6T-SRAM cell is designed to decrease the power utilization. The Auto Awake Mode is developed to control the entire 6T-SRAM cell design. The proposed 6T-SRAM- Auto Awake Mode (6T-SRAM-AAM) was implemented to reduce power utilization of understand and write down operation inside the 20 nm FinFET library. The experimental results showed the proposed 6T-SRAM-AAM design reduced power consumption of read & write operation up to 25% to 33.33% compared to existing Static RAM cells design.
Keyword: SRAM, low-power consumption,6T &7T- SRAM design, Auto Awake Mode.

Scope of the Article: Low-power design