Low Power and High Speed Full Adder using New XOR and XNOR Gates
PygastiJuveria1, K. Ragini2

1PygastiJuveria, student, G. Narayanamma institute of technology and science (for women), Hyderabad, (Telangana), India.
2Dr. K. Ragini, Professor, ECE Dept, G. Narayanamma institute of technology and science (for women), Hyderabad, (Telangana), India.

Manuscript received on 02 June 2019 | Revised Manuscript received on 10 June 2019 | Manuscript published on 30 June 2019 | PP: 1516-1519 | Volume-8 Issue-8, June 2019 | Retrieval Number: H6647058719/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Six hybrid full adder circuits using new XNOR, XOR gates are proposed in this paper. These circuits are designed to havehigh speed, and less power consumption compared to existing circuits. This is possible due to low output capacitance. Each one of the proposed full adder circuits has its own advantages of speed, power consumption and driving ability. Simulations are done in Tanner tool in 45-nm technology. From results, proposed circuits are found to be better thanexisting circuits. Also the performance of proposed full adder circuits is analysed by varying the supply voltage and output load.
Keyword: XOR-XNOR, full adder, transmission gate logic style, hybrid logic style, output driving capability.
Scope of the Article: Low-power design.