Delay Efficient Vedic Multiplier for DSP
Nidhi Gaur1, Anu Mehra2, Shikha Bathla3, Pradeep Kumar4
1Nidhi Gaur, Department of ECE, Amity University, Uttar Pradesh, India.
2Anu Mehra, Department of ECE, Amity University, Uttar Pradesh, India.
3Shikha Bathla, Department of ECE, Amity University, Uttar Pradesh, India.
4Pradeep Kumar, Department of ECE, Amity University, Uttar Pradesh, India.
Manuscript received on 20 August 2019 | Revised Manuscript received on 27 August 2019 | Manuscript Published on 26 August 2019 | PP: 499-501 | Volume-8 Issue-9S August 2019 | Retrieval Number: I10780789S19/19©BEIESP | DOI: 10.35940/ijitee.I1078.0789S19
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Multipliers are very essential blocks in any arithmetic and logic unit, accumulators and Digital signal processors. Due to the enlarging check on delay, design of faster multipliers is desired. Amidst numerous multipliers, Vedic multipliers are favored for their speed of operation. There are sixteen sutras in Vedic mathematics out of which four are multiplication techniques. “URDHVA TIRYAKBHYAM” is the most efficient vedic multiplication technique in terms of speed. In this paper we aim to develop a multiplier using Ripple Carry Adder and parallel prefix adders which carry out the “URDHVA TIRYAKBHYAM” sutra with improved speed of operation by providing the minimum delay for the multiplication of numbers regardless of their bit sizes. A vast majority of the engineering domain consists of ubiquitous technologies like DSP. As it is one of the most rapid growing technologies of the 21st Century, it faces challenges and improvisation at each step. Engineers are working diligently to improve the quality of Digital Signal processors and major breakthroughs are being made at a very good rate. Proposed multiplier could be applied for such DSP applications. Verilog language has been used for the coding. Xilinx Vivado Tool is used for synthesis and Model Sim 5.4 has been used for simulation.
Keywords: Urdhva Tiryakbhyam, Vedic Multiplier, Ripple Carry Adder, Parallel Prefix Adder.
Scope of the Article: Cryptography and Applied Mathematics