Delay Approximation Model for Prime Speed Interconnects in Current Mode
Naraiah R1, B. Balaji2, Erigela Radhamma3, Rajender Udutha4

1Naraiah R, Dept of ECE, Research Scholar, SSSUTMS, SEHORE, MP.
2B. Balaji, Dept of ECE, KLEF, Vaddeswaram, Guntur AP.
Erigela Radhamma, Dept of ECE, Brilliant Inst of Tech& sciences, Hyderabad, TS
4Rajender Udutha, Dept of ECE, Research Scholar at SSSUTMS, Bhopal

Manuscript received on 02 July 2019 | Revised Manuscript received on 09 July 2019 | Manuscript published on 30 July 2019 | PP: 3090-3093 | Volume-8 Issue-9, July 2019 | Retrieval Number: I8019078919/19©BEIESP | DOI: 10.35940/ijitee.I8019.078919

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Abstract: There is enormous demand for high speed VLSI networks in present days. The coupling capacitance and interconnect delay play a major role in judging the behavior of on chip interconnects. There is an on chip inductance effect as we switch to low technology that leads to delay in interconnecting. In this paper we are attempting to apply second order transfer function designed with finite difference equation and transform Laplace at the ends of the source and load termination. Analysis shows that the current signaling mode in VLSI interconnects provide better time delay than the voltage mode.
Keywords: VLSI Interconnect, Current Mode, Feedback Scheme.

Scope of the Article: Approximation and Randomized Algorithms