Design and Analysis of Gate All Around Tunnel FET based SRAM
Umesh Dutta1, M.K Soni2, Manisha Pattanaik3
1Umesh Dutta, Department of ECE, FET, Manav Rachna International Institute of Research and Studies, Faridabad, Haryana, India.
2M.K Soni, Department of ECE, FET, Manav Rachna International Institute of Research and Studies, Faridabad, Haryana, India.
3Manisha Pattanaik, Department of ICT, ABV-Indian Institute of Information Technology and Management, Gwalior, M.P, India.
Manuscript received on 30 June 2019 | Revised Manuscript received on 05 July 2019 | Manuscript published on 30 July 2019 | PP: 1492-1500 | Volume-8 Issue-9, July 2019 | Retrieval Number: I8237078919/19©BEIESP | DOI: 10.35940/ijitee.I8237.078919
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Tunnel FETs (TFETs) possess all required characteristics for replacing MOSFET device in circuits with stringent requirements particularly for Internet of Things (IoT) and Biomedical applications. In particular Gate-All-Around (GAA) TFET device configuration exhibits higher ION/IOFF ratio and strong control of the gate terminal over the channel. The main objective of this research work is to explore the prospects of using GAATFET device topology for designing low power and reliable SRAM cell. In this work both n-type and p-type Tunnel FET devices have been designed and simulated using Cogenda Visual TCAD tool. Verilog-A model relying on look up tables that are extracted through device simulations has been designed for performing circuit simulations of 6T and 8T SRAM cell involving these novel devices. Device simulation results show that both NTFET and PTFET devices exhibits excellent ION/IOFF ratio and steep subthreshold slope. NTFET device simulation results show 21.2 mV/decade of subthreshold slope and ION/IOFF ratio of 1013. PTFET device has ON current of the similar order as that of NTFET and has extremely low value of OFF current of less than 1 pA. Circuit simulation results show that by using optimized sizing of transistors in outward NTFET access transistor based 6T SRAM cell leads to reliable and fast read and write operation with acceptable values of noise margin. 6T TFET based SRAM cell achieves leakage power reduction by 77.5% in comparison to leakage power consumed by 8T TFET based SRAM thereby making it a favorable choice for memory design.
Keywords: Subthreshold Slope, Miller Capacitances, Leakage Current, Ambipolarity, BTBT model, Static Random Access Memory (SRAM), Leakage Current.
Scope of the Article: Mechanical Design