Low Power 32 x 32 – bit Reversible Vedic Multiplier
Ansiya Eshack1, S. Krishnakumar2
1Ansiya Eshack, Department of Electronics, School of Technology and Applied Sciences, Edapally, Ernakulam 682024
2S. Krishnakumar, Department of Electronics, School of Technology and Applied Sciences, Edapally, Ernakulam 682024
Manuscript received on 05 July 2019 | Revised Manuscript received on 09 July 2019 | Manuscript published on 30 August 2019 | PP: 852-856 | Volume-8 Issue-10, August 2019 | Retrieval Number: J90400881019/2019©BEIESP | DOI: 10.35940/ijitee.J9040.0881019
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Recently, low-power consuming devices are gaining demand due to excessive use and requirement of hand-held & portable electronic gadgets. The quest for designing better options to lower the power consumption of a device is in high-swing. The paper proposes two 32 x 32 – bit multipliers. The first design is based only on the Urdhava Tiryakbhyam Sutra of Vedic Mathematics. The use of this sutra has created a multiplier with higher throughput and lesser power utilization than conventional 32 x 32 – bit multipliers. The second design incorporates the reversible logic into the first design, which further reduces the power consumption of the system. Thus bringing together Vedic sutra for multiplication and reversible gates has led to the development of a Reversible Vedic Multiplier which has both the advantages of high-speed and low-power consumption.
Keywords: FPGA, High speed, Low power, Reversible Gates, Urdhava Tiryakbhyam Sutra, Vedic Multiplier.
Scope of the Article: Low-power design