Design a High Speed Multiplier using Two Phase PPA
Gajula Lakshminarayana1, Moparthy Gurunadha Babu2, Anupama A. Deshpande3

1Gajula Lakshminarayana, Ph.D Scholar, Shri Jagdishprasad Jhabarmal Tibrewala University, Jhunjhunu, Churela (Rajasthan), India. 

2Dr. Moparthy Gurunadha Babu, Professor & Dean, Department of ECE, CMR Institute of Technology, Hyderabad (Telangana), India.

3Dr. Mrs. Anupama A. Deshpande, Professor, Department of EEE, Shri Jagdishprasad Jhabarmal Tibrewala University, Jhunjhunu, Churela (Rajasthan), India.

Manuscript received on 05 September 2019 | Revised Manuscript received on 14 September 2019 | Manuscript Published on 26 October 2019 | PP: 146-149 | Volume-8 Issue-11S2 September 2019 | Retrieval Number: K102309811S219/2019©BEIESP | DOI: 10.35940/ijitee.K1023.09811S219

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Abstract: Basically, multiplier is an efficient superconductor logic which performs various switching operation. Here different types of adders are analysed using different methodologies. In this paper we introduced a multiplier using proposed PPA. It uses parallel prefix adders in their reduction phase and it is an effective system for faster results and optimised. The entire operation of proposed system depends upon three stages they are multiplier partial product generation, reduction stages and parallel prefix adder which is discussed in below sections. The delay gets reduced by achieving low logical depth in the system. So the Proposed system reduces the delay. From the proposed system we can observe that there is a reduction in delay and complexity. Compared to ripple carry adder and carry save adder, proposed system gives better results.

Keywords: PPA, VLSI, DSP, Partial Product Generation (PPG).
Scope of the Article: Low-power design