Modified LECTOR Technique for Level Shifters
G.V.S.R. Indraja1, T.V.S.Divakar2

1G.V.S.R. Indraja, Dept. of E.C.E, GMRIT, Rajam, Andhra Pradesh, India
2T.V.S.Divakar, Dept. of E.C.E, GMRIT, Rajam, Andhra Pradesh, India.

Manuscript received on 22 August 2019. | Revised Manuscript received on 07 September 2019. | Manuscript published on 30 September 2019. | PP: 1705-1708 | Volume-8 Issue-11, September 2019. | Retrieval Number: K15180981119/2019©BEIESP | DOI: 10.35940/ijitee.K1518.0981119
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Static power dissipation is a major problem in CMOS circuits and this is due to the increase in sub threshold leakage current which is the effect of voltage scaling and also leading to reducing the threshold voltage. Here we propose Lector technique to reduce the leakage current and at the same time it will not increase the dynamic power dissipation. Two leakage control transistors of which one is p-type and the other one is n-type were introduced into the logic gate. The source of one transistor controls the gate terminal of the other transistor. For any combination of input one of the two leakage control transistors will be near to its cutoff voltage by this the leakage currents can be minimized as the path resistance to ground will increase. For both idle and active states of circuit the proposed Lector technique is applicable which will result in more leakage reduction when compared to remaining techniques used for leakage reduction and it will also out pass the limitations Occurred due to the implementation of other power and delay reduction techniques. Experimental results indicate a delay is reduced by 50.3% and power is reduced by 94.4% for proposed level shifter circuits.
Keywords: Leakage power, transistor stacking, power optimization, Deep submicron, Level shifter.
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