Study of Sense Amplifier for Low offset High Speed SRAM Memory Design
Vishvender Singh1, Gunjan Agarwal2, Mukesh Sharma3
1Vishvender, Department of ECE, BSAITM, Faridabad (Haryana), India.
2Ms. Gunjan Agrwal, Assistant Professor, Department of ECE, BSAITM, Faridabad (Haryana), India.
3Mr. Mukesh Sharma, Assistant Professor, Department of ECE, BSAITM, Faridabad (Haryana), India.
Manuscript received on 6 April 2014 | Revised Manuscript received on 17 April 2014 | Manuscript Published on 30 April 2014 | PP: 127-132 | Volume-3 Issue-11, April 2014 | Retrieval Number: K16170431114/14©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The sense amplifiers is a main peripheral of CMOS memory and play an important role to overall delay, offset, speed , memory access time and power dissipation of the memory and to improve the speed performance of a memory, and to provide signals which conform to the requirements of driving peripheral circuits within the memory, sense amplifiers are applied. In this paper we present study and literature survey of low offset and high speed low power sense amplifier architecture selection for SRAM memory design application and in this paper also present the comparison voltage mode sense amplifier and current mode sense amplifier. Presented Sense amplifier CMOS schematic is design tanner EDA S-edit , Simulate T-spice and 0.13µm technology.
Keywords: Sense Amplifier, Current Mode Sense Amplifier, off Set, Intrinsic off Set.
Scope of the Article: High Speed Networks