Leakage Current Analysis of 6T & 7T-SRAM using FINFETs at 22nm Technology
N.Praveen Kumar1, B.Stephen Charles2, V.Sumalatha3

1N.Praveen Kumar*, ECE Department, JNTUA University, Kurnool, India.
2Dr.B.Stephen Charles, Principal, Stanley Stephen College of Engg & Tech, Kurnool, India.
3Dr.V.Sumalatha, Professor, JNTUA University, Anantapur, India.

Manuscript received on September 16, 2019. | Revised Manuscript received on 24 September, 2019. | Manuscript published on October 10, 2019. | PP: 2983-2986 | Volume-8 Issue-12, October 2019. | Retrieval Number: K22920981119/2019©BEIESP | DOI: 10.35940/ijitee.K2292.1081219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Persistent scaling of planar MOSFET results in increase in transistor package density and performance of chip. However at nanometer regime , it has become a very challenging issue due to the increase in the short channel effects. In nano scaled MOSFETs, the channel loses control from gate terminal due to potential at drain. Due to this, it is difficult to turn off MOSFET completely which inturn leads to leakage currents. Since cache memory occupies more area of processors, it is difficult to reduce leakage power in microprocessors. Double gate transistors have become replacement for MOS transistors at nano level. Since FINFETs have double gates, the leakage currents can be controlled effectively than planar MOSFET. In this paper, leakage currents of 6T & 7T-SRAM memory cell are analyzed using FINFETs at 22nm technology in hspice software
Scope of the Article: Renewable Energy Technology