Design, Implementation and Power Analysis of Low Voltage Heterojunction Tunnel Field Effect Transistor based Basic 6T SRAM Cell
B V V Satyanarayana1, M Durga Prakash2
1B V V Satyanarayana, Department of ECE, Koneru Lakshmaiah Education Foundation, Guntur, India.
2Dr. M Durga Prakash, Department of ECE, Koneru Lakshmaiah Education Foundation, Guntur, India.
Manuscript received on 27 August 2019. | Revised Manuscript received on 04 September 2019. | Manuscript published on 30 September 2019. | PP: 2898-2903 | Volume-8 Issue-11, September 2019. | Retrieval Number: K24370981119/2019©BEIESP | DOI: 10.35940/ijitee.K2437.0981119
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The battery-powered mobile devices limited energy process by MOSFET’s due to subthreshold swing and underneath 60mV/dec for ultra fewer energy applications. This research introduces the layout and execution of a mobile electronic device full-on-presence, extended Miller potential, and reduced HETT subthreshold swing effectiveness has been compared with MOSFET’s Gate oxide blending on source can increase channel tunneling in this work. To enhance transistor line, Miller capacitance impact can be decreased by using low band offset equipment and small power product of metals such as Ge or SiGe. This, in turn, leads to stronger transistor efficiency features. The proposed layout and execution of HETT includes manufacturing of mutually NHETT and PHETT and efficiency analyzes of both NHETT and PHETT. Concerning the fundamental and skeletal distinctions among MOSFET and HETT to promote the utilization of MOSFET instead of HETT, the benefits and constraints of both NHETT and PHETT have been detailed. HETT’s construction process is by no means entirely different, suitable for the scheme of MOS method and suitable for transportable motorized applications. HETT provides the 6T SRAM cell electricity evaluation and the output was reviewed using standard SRAM cell. The average power, maximum power and minimum power of SRAM by using both MOSFET and HETT are obtained and compared. The mask layers of HETT fabrication is not that much difference than MOSFET and hence CMOS MOSFET fabrication is friendly to HETT fabrication. In future, the combination of both CMOS MOSFET and HETT are used, CMOS technology for digital logic and HETT for semiconductor memory applications.
Keywords: Tunneling, Heterojunction, low power, SRAM, ultra-low voltage, band to band tunneling
Scope of the Article: Low-power design