A Low Power, High Speed 18-Transitor True Single-Phase Clocking D Flip- Flop Design In 90nm Cmos Technology
Shanti Kasani1, G.R.L.V.N. Srinivas Raju2

1Shanti Kasani, Design Engineer in Embedded Systems, John Deere India Pvt Ltd, Pune, Maharashtra, India. 
2Dr. G. R. L. V. N. Srinivasa Raju, Professor and HOD, Department of ECE, Shri Vishnu Engineering College for Women, Bhimavaram, A.P, India
Manuscript received on 27 August 2019. | Revised Manuscript received on 05 September 2019. | Manuscript published on 30 September 2019. | PP: 3258-3262 | Volume-8 Issue-11, September 2019. | Retrieval Number: K25310981119/2019©BEIESP | DOI: 10.35940/ijitee.K2531.0981119
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In this paper the authors came up with a contemporary low power, high-speed 18- transistor true singlephase clocking D flip-flop (FF) design using complementary pass-transistor logic. This design is a master-slave-type logic structure and hybrid logic design consisting of complementary pass-transistor logic style and static CMOS logic style. In order to reduce the number of transistors and to simplify the circuit complexity complementary pass-transistor logic style is used. In this design state transition is faster in the slave latch which enhances time performance using a virtual VDD technique. The circuit is designed using GPDK 90nm CMOS technology and the simulation results show better performance indices such as average power consumption, clock- to-Q delay, data-to-Q delay, PDP and area of utilization.
Keywords: low power, flip-flop, true single-phase clocking (TSPC), complementary pass-transistor logic (CPL).
Scope of the Article: Low-power design