Design and Analysis of Low Power SRAM using CMOS Technology
Krishan Chandra Mishra1, R.K. Singh2
1Krishan Chandra Mishra, Professor, Jagan Institute of Management Studies, (Delhi), India.
2R.K. Singh, Professor, Jagan Institute of Management Studies, (Delhi), India.
Manuscript received on 10 October 2019 | Revised Manuscript received on 24 October 2019 | Manuscript Published on 26 December 2019 | PP: 896-902 | Volume-8 Issue-12S October 2019 | Retrieval Number: L119910812S19/2019©BEIESP | DOI: 10.35940/ijitee.L1199.10812S19
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The power consumption in commercial processors and application specific integrated circuits increases with decreasing technology nodes. Power saving techniques have become a first class design point for current and future VLSI systems. These systems employ large on-chip SRAM memories. Reducing memory leakage power while maintaining data integrity is a key criterion for modern day systems. Unfortunately, state of the art techniques like power-gating can only be applied to logic as these would destroy the contents of the memory if applied to a SRAM system. Fortunately, previous works have noted large temporal and spatial locality for data patterns in commerical processors as well as application specific ICs that work on images, audio and video data. This paper presents a novel column based Energy Compression technique that saves SRAM power by selectively turning off cells based on a data pattern. This technique is applied to study the power savings in application specific inegrated circuit SRAM memories and can also be applied for commercial processors. The paper also evaluates the effects of processing images before storage and data cluster patterns for optimizing power savings.
Keywords: Low Power SRAM, SRAM, CMOS, Power Saving.
Scope of the Article: Low-power design