SEU Performance Enhancement in BPJLT Devices by Channel Doping and Film Thickness
N. Vinodhkumar1, C.Raja2, Satish Addanki3

1N.Vinodhkumar, Department of Electronics and Communication Engineering, Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology, Chennai, India.
2C.Raja, Professor, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, A.P., India,
3Satish Addanki*, Department of Electronics and Communication Engineering, Sasi Institute of Technology and Engineering, Aerodrome Road, Tadepalligudem, AP, India.

Manuscript received on September 16, 2019. | Revised Manuscript received on 24 September, 2019. | Manuscript published on October 10, 2019. | PP: 1857-1861 | Volume-8 Issue-12, October 2019. | Retrieval Number: L28651081219/2019©BEIESP | DOI: 10.35940/ijitee.L2865.1081219
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Abstract: The bulk planar junctionless transistor (BPJLT) is a potential candidate for future CMOS technologies due to its CMOS compatibility and scalability. In this paper, the impact of silicon film thickness and channel doping on single-event upset (SEU) radiation performance of BPJLT based SRAMs is studied using TCAD simulations. The simulation results show that BPJLT devices having higher channel doping and smaller film thickness provides the better SEU performance.
Keywords: BPJLT, SRAM, Threshold LET, SEU, TCAD.
Scope of the Article: Communication Engineering