Area efficient LFSR based ADC in 45nm Technology using verilog A
S.Karthik1, K.Priyadarsini2, Sarat Suhas3

1Karthik, Department of ECE, SRMIST, Vadapalani, Chennai India.
2K.Priyadarsini, Department of CSE, VISTAS, Pallavaram, Chennai India.
3Sarat Suhas, Department of ECE, SRMIST, Vadapalani, Chennai India. 

Manuscript received on September 17, 2019. | Revised Manuscript received on 23 September, 2019. | Manuscript published on October 10, 2019. | PP: 2460-2463 | Volume-8 Issue-12, October 2019. | Retrieval Number: L29831081219/2019©BEIESP | DOI: 10.35940/ijitee.L2983.1081219
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Abstract: Data converters are very much useful in this modern world for circuit design at both ends i.e., transmitter end and receiver end. This paper primarily aims at reducing the overall area of the 8 bit ADC by decreasing the size of traditional counter with replacement of LFSR which uses few XOR gates and FFs. Another advantage of using LFSR is that it produce random states which may result in reducing the conversion time or in other words speeding up the ADC. Verilog A is used for implementing the ADC since it uses high level behavior model which allows to use simple equation to describe complex issues, a Standard language, Easy to learn and use and Flexible for both analog and AMS application Verilog A is much more simple than Spice C code. Linear feedback shift register is employed in the implementation of ADC as it fewer components than binary counter. The proposed ADC architecture is implemented and simulated using Cadence 0.45 µm tool and compared with Standard ADC which uses traditional binary counter. Results show that there is almost 50% in power savings when compared to the traditional ADC designs.
Keywords: ADC, Area Efficient, Data Converters, Verilog a, Linear Feedback Shift Register, Signal flow system.
Scope of the Article: Signal Control System & Processing