Area and Power Potent VLSI Architecture for Modified CSLA with A Logic Optimization Technique
Bala Sindhuri Kandula1, K.Padma Vasavi2, I.Santi Prabha3
1Bala Sindhuri Kandula,E.C.E Department, Ph.D Scholar, JNTU, Kakinada, Andhra Pradesh, India.
2K.Padma Vasavi , Professor,E.C.E Department , SVECW , Bhimavaram Andhra Pradesh , India.
3I. Santi Prabha, Professor , E.C.E Department, University College of Engineering, JNTU, Kakinada.
Manuscript received on September 16, 2019. | Revised Manuscript received on 24 September, 2019. | Manuscript published on October 10, 2019. | PP: 2873-2879 | Volume-8 Issue-12, October 2019. | Retrieval Number: L30511081219/2019©BEIESP | DOI: 10.35940/ijitee.L3051.1081219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Through generations, in an endeavor to pioneer innovative circuit designs, an adder is having the greatest importance as it is a basic building block to decide the system’s overall performance. Wide varieties of adders are used for a plethora of applications in the field of Signal Processing and VLSI systems. Most predominantly used Speed efficient architecture for performing n-bit addition in VLSI applications is Square Root Carry Select Adder (SQRT-CSLA) as it pre-computes the carry and sum by assuming input carry as ‘zero’ and ‘one’. But the overall area usage is high as it uses more number of full adders when compared to Ripple Carry Adder. Though, the existing adder designing techniques are area efficient, there is still scope to achieve area efficiency as area decides the cost of the VLSI Systems. Not only area-efficient but also power potent architectures are required to accelerate the overall performance of the VLSI systems. To meet these objectives, this paper proposes an efficient VLSI architecture for carry select adder by using logic optimization technique addressing performance constraints. The proposed architecture is designed and implemented using cadence encounter tool for different data widths ranging from 16 bits to 128 bits. The performance of the proposed 128-bit architecture achieves an area improvement of 63.43% and a power improvement of 71.00923% when compared to 128-bit SQRT-CSLA architecture
Keywords: Area Efficiency, CSLA, Logic Optimization, VLSI Adder.
Scope of the Article: Computer Architecture and VLSI